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The memory tester components for the design are Verilog HDL components with an accompanying Hardware Component Description File ( _hw.tcl) that describes the interfaces and parameterization of each component. The final design includes various Qsys components that generate test data, access memory, and verify the returned data. The final system contains the SDRAM controller and instantiates a Nios ® II processor and embedded peripherals in a hierarchical subsystem. In this tutorial, you create a memory tester system that tests a synchronous dynamic random access memory (SDRAM) device. It guides you through system requirement analysis, hardware design tasks, and evaluation of the system performance, with emphasis on system architecture.
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This tutorial shows you how to design a system that uses various test patterns to test an external memory device. This tutorial introduces you to the Qsys system integration tool available with the Quartus ®II software.
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